`timescale 1ns / 1ps

module top(
    input clk,
    input rst,
    input [31:0] data_in,
    output [31:0] data_out,
    output valid
);

wire [31:0] intermediate_data;
wire intermediate_valid;
wire [7:0] short_signal;
wire very_long_signal_name_for_testing_alignment;

sub_module_1 u_sub1 (
    .clk(clk),
    .rst(rst),
    .data_in(data_in),
    .data_out(intermediate_data),
    .valid(intermediate_valid),
    .short(short_signal),
    .long_sig(very_long_signal_name_for_testing_alignment)
);

sub_module_2 u_sub2 (
    .clk(clk),
    .reset(rst),
    .din(intermediate_data),
    .dout(data_out),
    .valid_in(intermediate_valid),
    .valid_out(valid),
    .s(short_signal),
    .vl(very_long_signal_name_for_testing_alignment)
);

endmodule

module sub_module_1(
    input clk,
    input rst,
    input [31:0] data_in,
    output [31:0] data_out,
    output valid,
    output [7:0] short,
    output long_sig
);
endmodule

module sub_module_2(
    input clk,
    input reset,
    input [31:0] din,
    output [31:0] dout,
    input valid_in,
    output valid_out,
    input [7:0] s,
    input vl
);
endmodule
